(1) Field of the Invention
The invention relates to silicon-on-insulator (SOI) devices and, more particularly, to a method to form a SOI device having improved ESD performance.
(2) Description of the Prior Art
At present, the vast majority of integrated circuit products are formed on bulk semiconductor wafers. However, silicon-on-insulator (SOI) wafer-based products are under development as a majority technology for the future. SOI offers the advantages of improved short channel performance, improved isolation, and reduced power supply capability. However, ESD protection of SOI devices remains a significant challenge to manufacturers.
Referring now to FIG. 1, an example of a prior art SOI MOSEET is shown. The SOI substrate comprises a buried oxide layer 14, typically many microns thick, that is formed overlying a substrate 10. A silicon layer is formed overlying the buried oxide layer 14. In this case, the silicon layer has been doped to form an N+ source 26, an N+drain 22, and a P—body region 34 for a MOS transistor. A typical gate 30 is formed overlying the body region 34 between source 26 and drain 22. Shallow trench isolations (STI) 1B are formed through the silicon layer to the buried oxide layer 14 to isolate the MOS device.
The typical SOI NMOS transistor shown differs from a bulk version NMOS due to the presence of the buried oxide layer 14 underlying the MOS device. The buried oxide layer 14 provides excellent device isolation while facilitating the formation of MOS devices having improved short-channel capabilities. Note that the N+ drain 22 is coupled to an I/O pad for the integrated circuit device. Therefore, this transistor must be able to withstand ESD events due to external handling and/or external conditions. However, the presence of the buried oxide layer 14 may have detrimental effects for the ESD performance of the device.
During an ESD event, the drain 26 to body 34 junction will exhibit a reverse breakdown when the junction breakdown voltage is exceeded. Significant current will flow through the device. To prevent damage to the MOS device and to other parts of the overall integrated circuit, it is essential that the energy of the ESD pulse be dissipated. In a bulk MOS device, a part of this energy dissipation will occur in the bulk silicon material of the substrate. In the SOI, device, however, the buried oxide layer 14 blocks current flow into the bulk substrate 10. Further, the buried oxide layer 14 has a low thermal conductivity compared to silicon (about {fraction (1/10)} as large as silicon). Therefore, the buried oxide layer 14 tends to display excessive heating due to current flow. In addition, the absence of a bulk current path causes current concentration near the surface of the MOS channel where excessive energy dissipation can cause damage. Finally, the relative energy dissipation in the device is proportional to the reverse breakdown voltage of the N+ drain 22 to P—body 34 junction. It is found that the SOI MOSFET device displays a lower power-to-failure curve than a bulk-substrate MOSFET. A method of improving the ESD performance of the SOI MOS device would represent a significant step forward in the development of SOI as a majority technology.
Several prior art inventions relate to the ESD performance of SOI devices. U.S. Pat. No. 6,242,763 to Chen et al teaches a silicon-controlled rectifier (SCR) device for a SOI process. The SCR adds an N+/P+ zener diode to the prior SCR to reduce the trigger voltage. U.S. Pat. No. 6,222,710 to Yamaguchi discloses an ESD device in a SOI process where at least one MOS transistor is coupled to the external terminal by a forward bias. Another MOS transistor is also coupled to the terminal by reverse bias. U.S. Pat. No. 6,143,594 to Tsao et al describes a bulk silicon ESD protection scheme compatible with low voltage CMOS processing. U.S. Pat. No. 6,133,078 to Yun teaches a method to manufacture a bulk semiconductor device having an ESD protection region. Several impurity layers are implanted into the ESD region to improve ESD performance. U.S. Pat. No. 6,034,399 to Brady et al discloses an ESD device for use in a SOI system. The ESD device is formed in a bulk region to protect other devices formed in the SOI region. U.S. Pat. No. 5,982,003 to Hu et al teaches a SOI MOSFET having a low barrier body contact under the source region. An improvement in ESD performance of the device is cited.